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combined with a vco (tuner), the mgp 3006x6 device, with four hard-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with pll-frequency synthesis tuning. the pll permits precise crystal-controlled setting of the frequency of the tuner oscillator between 16 and 1300 mhz in increments of 62.5 khz, and, with a 2.4-ghz prescaler 1/2, in the tv-sat band in increments of 125 khz. the tuning process is controlled by a microprocessor via an i 2 c bus. the i 2 c bus noise immunity has been improved by a factor of 10 compared to the sda 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing the higher-order harmonics, which reduces the moir noise considerably. type ordering code package mgp 3006x6 q67000-h5113 p-dso-16-1 (smd) mgp 3006x6 Q67006-H5113 p-dso-16-1 tape & reel (smd) ghz pll with i 2 c bus and four chip addresses bipolar ic mgp 3006x6 p-dso-16-1 features l 1-chip system for mpu-control ( i 2 c bus) l 4 programmable chip addresses l short pull-in time for quick channel switch-over and optimized loop stability l 3 high-current band switch outputs (20 ma) l software-compatible with sda 3202 series l oxis iii technology semiconductor group 1 04.93
semiconductor group 2 mgp 3006x6 circuit description tuning section uhf/vhf the tuner signal is capacitively coupled at the uhf/vhf-input and subsequently amplified. ref the reference input ref should be decoupled to ground using a capacitor of low series inductance. the signal passes through an asynchronous divider with a fixed ratio of p = 8, an adjustable divider with ratio n = 256 through 32767, and is then compared in a digital frequency/phase detector to a reference frequency f ref = 7.8125 khz. q1, q2 this frequency is derived from a balanced, low-impedance 4-mhz crystal oscillator (pin q1, q2) by dividing its output signal by q = 512. the phase detector has two outputs up and down that drive the two current sources i+ and iC of a charge pump. if the negative edge of the divided vco-signal appears prior to the negative edge of the reference signal, the i+ current source pulses for the duration of the phase difference. in the reverse case the iC current source pulses. pd, ud if the two signals are in phase, the charge pump output (pd) goes into the high-impedance state (pll is locked). an active low-pass filter integrates the current pulses to generate the tuning voltage for the vco (internal amplifier, external output transistor at ud and external rc-circuitry). the charge pump output is also switched into the high-impedance state when the control bit t0 = 1. here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. ud may be switched off by the control bit os to allow external adjustments. by means of a control bit 5i the pump current can be switched between two values by software. this programmability permits alteration of the control response of the pll in the locked-in state. in this way different vco-gains in the different tv-bands can be compensated, for example. p0, p1, p2 the software-switched outputs p0, p1, p2 can be used for direct band selection (20 ma current output). p4, p7 p4 and p7 are general-purpose open-collector outputs. the test bit t1 = 1 switches the test signal cy (divided input signal) to p7. cau four different chip addresses can be set by appropriate connection of pin cau.
mgp 3006x6 semiconductor group 3 i 2 c bus interface data are exchanged between the processor and the pll on the i 2 c bus. scl, sda the clock is generated by the processor (input scl), while pin sda works as an input or output depending on the direction of the data (open collector; external pull-up resistor). both inputs have hysteresis and a low-pass characteristic, which enhances the noise immunity of the i 2 c bus. the data from the processor pass through an i 2 c bus control. depending on their function the data are subsequently stored in registers. if the bus is free, both lines will be in the marking state (sda, scl are high). each telegram begins with the start condition and ends with the stop condition. start condition: sda goes low, while scl remains high. stop condition: sda goes high while scl remains high. all further information transfer takes place during scl = low, and the data is forwarded to the control logic on the positive clock edge. the table bit allocation should be referred to in the following paragraph. all telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the sda-line to low (acknowledge condition). the first byte is comprised of seven address bits. these are used by the processor to select the pll from several peripheral components (chip select). the eighth bit is always low. in the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. in each case the second byte of the same data type or a stop condition has to follow the first byte. v s , gnd when the supply voltage is applied a power-on reset circuit prevents the pll from setting the sda-line to low, which would block the bus.
semiconductor group 4 mgp 3006x6 circuit description (contd) bit allocation divider ratio n = 16384 n14 + 8192 n13 + 4096 n12 + 2048 n11 + 1024 n10 + 512 n9 + 256 n8 + 128 n7 + 64 n6 + 32 n5 + 16 n4 + 8 n3 + 4 n2 + 2 n1 + n0 band selection p0, p1, p2, p4, p7 = 1 open-collector output is active. pump current programming 5i = 1 high current ud disable os = 1 ud is disabled. test mode t1, t0 = 0, 0 normal operation t1 = 1 p3 = f ref ; p4 = cy t0 = 1 tristate: charge pump output pd is in high-impedance state. msb a = acknowledge address byte 1 1 0 0 0 ma1 ma0 0 a prog. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 a prog. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 a control info. byte 1 1 5i t1 t0 x x 1 os a control info. byte 2 p7 x x p4 x p2 p1 p0 a
mgp 3006x6 semiconductor group 5 chip address switching telegram examples start-addr-dr1-dr2-cw1-cw2-stop start = start condition start-addr-cw1-cw2-dr1-dr2-stop addr = address start-addr-dr1-dr2-cw1-stop dr1 = divider ratio 1st byte start-addr-cw1-cw2-dr1-stop dr2 = divider ratio 2nd byte start-addr-dr1-dr2-stop cw1 = control word 1st byte start-addr-cw1-cw2-stop cw2 = control word 2nd byte start-addr-dr1-stop stop = stop condition start-addr-cw1-stop ma1 ma0 voltage at cau 0 0 (0 0.1) v s 0 1 open-circuit 1 0 (0.4 0.6) v s 1 1 (0.9 1) v s
semiconductor group 6 mgp 3006x6 pin configuration (top view)
mgp 3006x6 semiconductor group 7 pin definitions and functions pin no. symbol function 1 pd input active filter/charge pump output 2 q1 quartz crystal 3 q2 quartz crystal 4 sda data input/output for i 2 c bus 5 scl clock input for i 2 c bus 6 p7 port output (open collector) 7 p4 port output (open collector) 8 cau address switch input 9 p2 port output (open collector) 10 p1 port output (open collector) 11 p0 port output (open collector) 12 v s supply voltage 13 uhf/vhf signal input 14 ref amplifier reference input 15 gnd ground 16 ud output active filter
semiconductor group 8 mgp 3006x6 block diagram
mgp 3006x6 semiconductor group 9 absolute maximum ratings t a = C 20 to 80 c parameter symbol limit values unit remarks min. max. supply voltage v s C 0.3 6 v output pd v 1 C 0.3 v s v crystal oscillator pins q1, q2 v 2 C 0.3 v s v bus input/output sda v 4 C 0.3 6 v bus input scl v 5 C 0.3 6 v port outputs p0, p1, p2, p4, p7 v 6 C 0.3 16 v chip address switch cau v 8 C 0.3 v s v signal input uhf/vhf v 13 C 0.3 0.3 v for v s = 0 v reference input ref v 14 C 0.3 0.3 v for v s = 0 v output active filter ud v 16 C 0.3 v s v bus output sda i 4l C 1 5 ma open collector port outputs p0, p1, p2 i 9l C 1 20 ma open collector port outputs p4 p7 i 7l i 6l C1 C1 5 7 ma ma open collector open collector total port output current s i l 25 ma junction temperature t j 125 c storage temperature t stg C 40 125 c thermal resistance (junction to ambient) r th ja 125 k/w
semiconductor group 10 mgp 3006x6 operating range supply voltage v s 4.5 5.5 v ambient temperature t a C20 80 c input frequency f 13 16 1300 mhz (at 25 c) crystal frequency f 2 3.2 4.8 mhz programmable divider factor n 256 32767 ac/dc characteristics t a = C 20 to 80 c; v s = 4.5 to 5.5 v parameter symbol limit values unit test condition test circuit min. typ. max. supply current i s 41 55 ma v s = 5 v 1 crystal oscillator connections q1, q2 oscillation frequency f 2 3.99975 4.000 4.00025 mhz f q = 4 mhz 1 margin from 1st (fundamental) to 2nd and 3rd harmonics 1) 20 db signal input uhf/vhf sensitivity a 13 a 13 a 13 e 27/10 e 27/10 e 20/22 3/315 3/315 3/315 dbm/ 2) dbm/ 2) dbm/ 2) f 13 = 70 500 mhz f 13 = 1000 mhz f 13 = 1100 mhz 2 2 2 port outputs p0, p1, p2 (switch with open collector) h-output current i 9h 10 m a v 6h = 13.5 v 3 l-output voltage v 9l 0.5 v i 6l = 20 ma 3 notes see page 11. absolute maximum ratings (contd) t a = C 20 to 80 c parameter symbol limit values unit remarks min. max.
mgp 3006x6 semiconductor group 11 1) design note only: no 100 % final inspection. 2) mvrms into 50 w. 3) ripple voltage on tuning line ( see application circuit ) = 128 m s ( i 1z + i 16 / b 2 )( c 1 + c 2 ) / ( c 1 c 2 ) e.g. for i 16 = 8 m a, c 1 = 180 nf, c 2 = 9 pf, worst-case ripple voltage = 61 m a. port outputs p4, p7 (switch with open collector) h-output current i 6h 10 m a v 6h = 13.5 v 4 l-output voltage v 6l 0.5 v i 6l = 1.7 ma 4 phase-detector output pd ( v s = 5 v) pump current pump current i 1h i 1h 90 22 220 50 300 75 m a m a 5i = 1; v 1 = 2 v 5i = 0; v 1 = 2 v 5 5 tristate current 3) i 1z C 3 1 3 na t1 = 1; v 1 = 2 v 5 current gain from pd to ud 3) b 2 6400 t1 = 1; v 1 = 2 v; i 1 = 2 na 5 output voltage v 1l 1.0 2.5 v locked 5 active filter output ud (test mode t0 = 1; pd = tristate) output current C i 16 500 m a v 16 = 0.8 v; i 1h = 90 m a 5 output voltage output voltage v 16 v 16 100 500 mv mv v 1l = 0 v os = 1; v s = 5 v; t a = 25 c 5 5 chip address switch cau input current input current i 8h C i 8l 50 50 m a m a v 8h = 5 v v 8l = 5 v 7 7 ac/dc characteristics (contd) t a = C 20 to 80 c; v s = 4.5 to 5.5 v parameter symbol limit values unit test condition test circuit min. typ. max.
semiconductor group 12 mgp 3006x6 ac/dc characteristics t a = C 20 to 80 c; v s = 4.5 to 5.5 v; refer to test circuit 6 parameter symbol limit values unit test condition min. typ. max. bus inputs scl, sda h-input voltage v 4ih 3 5.5 v l-input voltage v 4il 1.5 v h-input current i 4ih 10 m a v 4ih = v s l-input current C i 4il 20 m a v 4il = 0 v bus output sda (open collector) h-output current i 4oh 10 m a v 4oh = 5.5 v l-output voltage v 4ol 0.4 v i 4ol = 3 ma edges scl, sda rise time t r 1 m s fall time t f 0.3 m s shift clock scl frequency f 5 0 100 khz h-pulse width t 5high 4 m s l-pulse width t 5low 4.7 m s start set-up time t susta 4.7 m s hold time t hdsta 4 m s notes see page 19
mgp 3006x6 semiconductor group 13 1) design note only: no 100 % final inspection. stop set-up time t susto 4.7 m s bus free t buf 4.7 m s data transfer set-up time t sudat 0.25 m s hold time t hddat 0 m s input hysteresis scl, sda 1) 300 mv low-pass cutoff frequency scl, sda 1) 500 khz ac/dc characteristics (contd) t a = C 20 to 80 c; v s = 4.5 to 5.5 v; refer to test circuit 6 parameter symbol limit values unit test condition min. typ. max.
semiconductor group 14 mgp 3006x6 test circuit 1 crystal oscillator
mgp 3006x6 semiconductor group 15 test circuit 2 measurement of input sensitivity calibration of signal generator
semiconductor group 16 mgp 3006x6 test circuit 3 test circuit 4 test circuit 5
mgp 3006x6 semiconductor group 17 test circuit 6 i 2 c bus timing diagram set-up time (start) t susta hold time (start) t hdsta h-pulse width (clock) t high l-pulse width (clock) t low set-up time (data transfer) t sudat hold time (data transfer) t hddat set-up time (stop) t susto bus free time t buf fall time t f rise time t r all times related to 10 % and 90 % values.
semiconductor group 18 mgp 3006x6 test circuit 7 application circuit
mgp 3006x6 semiconductor group 19 notes 1. loop bandwidth w r = ? [( i p k vco ) / ( c 1 p n )] attenuation a = 0.5 w r r c 1 with i p = charge pump current k vco = vco-gain r , c 1 = loop filter component values p = prescaler division ratio n = programmable division ratio e.g. i p = 50 m a, k vco = 18.7 mhz/v, r = 22 k w , c 1 = 180 nf, p = 8, n = 11520 (channel 47): w r = 237 hz, f r = 38 hz, a = 0.47 typically, c 2 = c 1 /5. 2. symmetrical capacitive coupling improves the balance of the crystal oscillator and thus reduces cross-talk. 3. high-impedance port outputs and the address selection input p3 can be decoupled from external noise with a 1 nf capacitor. 4. it is important to keep to the i 2 c bus specification concerning maximum capacitance and impedance.
semiconductor group 20 mgp 3006x6 diagrams sensitivity at uhf/vhf-input i 2 c bus noise immunity sinusoidal noise pulses are applied via a coupling capacitance of 33 pf to the scl- and sda-inputs.
mgp 3006x6 semiconductor group 21 plastic package, p-dso-16-1 (smd) (plastic dual small outline) gps05119 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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